Release notes
Release notes
Review what changed and which platform-specific checks and limitations apply to each published preview.
HDL Ripper v0.1.8
September 16, 2026
Windows · x64
Preliminary desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; drag and resize states, edit transition curves, and save/reopen without coordinate drift. Includes real counter simulation and verified update downloads. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.7
September 13, 2026
Windows · x64
Preliminary desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; drag and resize states, edit transition curves, and save/reopen without coordinate drift. Includes real counter simulation and verified update downloads. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.6
September 10, 2026
Windows · x64
Preliminary desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; drag and resize states, edit transition curves, and save/reopen without coordinate drift. Includes real counter simulation and verified update downloads. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Apple silicon
Preliminary Mac desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; edit curves and save/reopen without coordinate drift. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Intel
Preliminary Mac desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; edit curves and save/reopen without coordinate drift. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.5
September 7, 2026
Windows · x64
Preliminary desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; drag and resize states, edit transition curves, and save/reopen without coordinate drift. Includes real counter simulation and verified update downloads. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Apple silicon
Preliminary Mac desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; edit curves and save/reopen without coordinate drift. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Intel
Preliminary Mac desktop build: HDL-owned FSMs with names fitted inside states, editable fonts, colors, fills and borders, and navigation into nested states. Import source-bound HDL Designer FSM layouts and appearance; edit curves and save/reopen without coordinate drift. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Full structural HDL Designer conversion, exact legacy rendering fidelity, signal splitting and nested block authoring remain unfinished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.4
September 7, 2026
Windows · x64
Preliminary desktop build: zoom diagrams with Ctrl+wheel, drag and style ports and blocks, and resize FSM states. Layout edits persist in HDL comments with Undo and save/reopen support. Includes real counter simulation and automatic verified update downloads with a compact Update action. Signal splitting, nested blocks, editable FSM transition points and HDL Designer import remain unfinished.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Apple silicon
Preliminary Mac desktop build: zoom diagrams with Cmd/Ctrl+wheel, drag and style ports and blocks, and resize FSM states. Layout edits persist in HDL comments. Includes the selected-port screenshot correction and automatic verified update downloads with a compact Update action. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Signal splitting, nested blocks, editable transition points and HDL Designer import are not finished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Intel
Preliminary Mac desktop build: zoom diagrams with Cmd/Ctrl+wheel, drag and style ports and blocks, and resize FSM states. Layout edits persist in HDL comments. Includes the selected-port screenshot correction and automatic verified update downloads with a compact Update action. Native Mac installation and headless simulation are checked; complete Mac annotation and app-driven installation/relaunch verification remain open. Signal splitting, nested blocks, editable transition points and HDL Designer import are not finished.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.3
September 6, 2026
macOS · Apple silicon
Experimental Mac desktop preview: dark HDL editing, folding, source-linked diagrams, counter recognition and real quick simulation using installed Icarus Verilog tools. Native Mac installation and headless simulation are checked; interactive reporting and update-byte verification use the same-source Linux desktop. Please read the platform limitations before testing.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Intel
Experimental Mac desktop preview: dark HDL editing, folding, source-linked diagrams, counter recognition and real quick simulation using installed Icarus Verilog tools. Native Mac installation and headless simulation are checked; interactive reporting and update-byte verification use the same-source Linux desktop. Please read the platform limitations before testing.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.2
September 6, 2026
Windows · x64
Experimental desktop build: dark HDL editing with folding and counter recognition, source-linked schematic/FSM navigation, and compact measured counter simulations with editable inputs saved in HDL comments. Includes native file editing, private annotated bug reports, offline retry and signed-update downloads. This is not the completed HDL workbench.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- Quick simulation currently supports recognized SystemVerilog counters and requires Icarus Verilog (iverilog and vvp) installed on PATH. The installer does not include a simulator.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Apple silicon
Experimental Mac desktop preview: dark HDL editing, folding, source-linked diagrams, counter recognition and real quick simulation using installed Icarus Verilog tools. Native Mac installation and headless simulation are checked; interactive reporting and update-byte verification use the same-source Linux desktop. Please read the platform limitations before testing.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
macOS · Intel
Experimental Mac desktop preview: dark HDL editing, folding, source-linked diagrams, counter recognition and real quick simulation using installed Icarus Verilog tools. Native Mac installation and headless simulation are checked; interactive reporting and update-byte verification use the same-source Linux desktop. Please read the platform limitations before testing.
Platform limitations
- Experimental macOS build: native installation, headless analysis and real counter simulation were checked on this architecture. Interactive desktop journeys were checked on Linux, not macOS.
- The app is ad-hoc signed, not Apple Developer ID-signed or notarized. Normal macOS launch protections still apply.
- Native macOS UI capture permissions and automatic update installation remain unverified. Update signatures and downloads were checked using the installed Linux desktop without installing the Mac payload there.
- Quick simulation requires Icarus Verilog (iverilog and vvp) on the app process PATH. The installer does not include a simulator; launching from a configured terminal may be necessary.
- Full HDL coverage, general process simulation, behavioral models, bundle/module authoring tools and the complete unified editor remain in development.
HDL Ripper v0.1.1
September 6, 2026
Windows · x64
Experimental desktop build for early testing: native HDL file editing, selected-image bug reports, annotations, offline retry and signed-update downloads. This is not the completed HDL workbench.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- The accepted diagram/editor redesign, full HDL coverage and real simulation remain in development.
HDL Ripper v0.1.0
September 6, 2026
Windows · x64
Experimental desktop build for early testing: native HDL file editing, selected-image bug reports, annotations, offline retry and signed-update downloads. This is not the completed HDL workbench.
Platform limitations
- Experimental Windows build: native Windows graphics and UI capture have not been verified. Desktop interactions were tested on Linux.
- Installation and upgrades were exercised under Wine. Fresh WebView2 installation and client-driven Windows restart remain unverified.
- The Windows installer is not Authenticode-signed. App updates require the embedded publisher verification key.
- The accepted diagram/editor redesign, full HDL coverage and real simulation remain in development.